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by Peter Dzwig
Tilera first made a name for itself a couple of years ago with the Tile64, which we wrote about at the time. Now Tilera have announced the Gx series of "tile"-based processors. A development of the earlier Tile64 and TilePro chips, the Tile Gx can have from 16 to 100 tile processors on the chip. These form a homogeneous array of 64-bit VLIW processors with a 64-bit instruction bundle, interconnected by a mesh network. The pipeline is three-deep and can handle up to three instructions per cycle. The whole is programmable using C or C++ via the GCC compiler, and can run Linux. Tilera have an Eclipse-based IDE.
Claiming to be “the world's first 100-core processor” and to “offer the highest performance of any microprocessor yet announced by a factor of four” the PR is a little over-hyped. However the Tile Gx is likely to be an important chip in its target sectors. This is essentially the embedded markets covering the gamut of high performance applications such as advanced networking, wireless infrastructure and digital video. These don't surprise any Tiler-watcher. However the addition of Cloud computing as an applications area shows that they are starting to move away from their traditional markets to look more broadly. All that the PR says is that suitable applications may lie in areas such as LAMP servers, data caching and databases. Whether this means that anyone is already running a corporate database on a Tile system is not made explicit. There are, though, applications in databases and data processing applications which are well-suited to multiple data pipelines.
The Gx does appear to offer some real performance leaps and some very interesting architectural novelties. The 100-core angle is really just what it says. We would be hard pressed to think of another processor with 100 cores, 80 yes (Intel Terascale), 90 yes (Cisco), over 100 yes (many of them, some even saw the light of commercial day); but exactly 100? We can't think of one for which you could produce a product spec-sheet! The Tile Gx series comprises Gx16 (16 cores, 4x4), Gx36 (36 cores, 6x6), Gx64 (64 cores, 8x8), and the Gx100 which unsurprisingly has 100 cores in a 10x10 grid. The performance claims will need some practical justification, but that will have to wait till silicon is available.
Although the chips arrange the tile processors in a regular 2-dimensional array, problems do not always fit such a structure. The Gx series has routing capabilities to get round this: the programmer can build appropriate networks of processors with the cores and the interconnect and do that without compromising performance. If you look at most applications where you are into proper parallel processing, i.e. mapping directly between cores and algorithm components, then you end up with irregular networks. This is why Tilera's local memory structure (32K L1i, 32K L1d, 256K L2 per tile) is appropriate in a very general purpose architecture.
Sadly you can't expect to see the Gx in your friendly local distributor's catalogue soon. The Gx36 is slated for introduction around Q4 2010 – which the experienced among you may interpret as you see fit. We will though be writing more about the Gx series soon.