Mobile Communications, picoChip and MCPs
This week sees the Mobile Industry’s annual get-together, The Mobile World Congress – formerly 3GSM – in Barcelona. Among the many participants is UK-based picoChip. They have just announced their PC8808 reference design, which represents the first fruits of its new Beijing design office, as well as collaborations with mimoOn and Continuous Computing. In the none too distant past picoChip announced input of funds from Samsung as well as its PC20x range. Red Herring named picoChip in its “Global 100” awards last year. Clearly a small British company expanding to play a global role. Why is this interesting to us? Because the heart of picoChip&rlquo;s products is a massively-parallel multicore architecture.
The company has established itself in a relatively few years in the market as probably the leader in picocell and femtocell technologies, certainly as far as multicore goes, and provides a broad spread of support for a variety of communications technologies.
The PC20x is a family of massively parallel core-arrays. The cores are Long Instruction Word (LIW) DSP engines capable of six operations per cycle, giving a claimed 230GIPS. Each core has access to local memory and to off-chip DRAM. In the PC203 there are 248 array elements, of which 196 are standard elements and the other 52 are for functions such as control and memory access. All the elements are connected via linear buses and “switch matrix” cores. The whole is, as picoChip likes to put it, “tuned for wireless” applications. The arrays have specialised coprocessors to handle wireless-standard mandated tasks such as encryption, Fast Fourier Transforms (FFTs), correlation and other functions. The processors can be attached to a control processor (PC203) or in the case of the PC 202 and 205 contain an ARM processor. The whole is programmable in C – or assembler if you really must!
Our interest in the design of these chips is because they are typical of the High Functionality Computing (HFC) application of MCPs that we have written of previously, with multiple cores at the centre, and specialised engines addressing specific requirements
Such HFC embedded processors represent the deployment of the lessons of traditional HPC to embedded processor design. With Tilera’s announcement of its 64-processor engine last autumn and various other communications-oriented engines such as IBM’s Cell and Cisco’s CRS, we are seeing MCPs appearing with ever-increasing regularity in the comms space. These HFC engines are not just demonstration prototypes, they are being deployed in the sort of everyday applications that affect all of us. If that were not enough, there are persistent rumours that mobile phone manufacturers will move to using HFC-style designs in merchant handsets in the not too distant future.